A JPEG Chip for Image Compression and Decompression
Journal of VLSI Signal Processing Systems
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DCC '97 Proceedings of the Conference on Data Compression
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A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor
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Analog Integrated Circuits and Signal Processing
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Computer Networks: The International Journal of Computer and Telecommunications Networking
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Proceedings of the 4th international conference on Embedded networked sensor systems
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Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microprocessors & Microsystems
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Computer Networks: The International Journal of Computer and Telecommunications Networking
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IEEE Transactions on Information Theory
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IEEE Transactions on Consumer Electronics
IEEE Communications Magazine
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International Journal of Ad Hoc and Ubiquitous Computing
Journal of Systems Architecture: the EUROMICRO Journal
Low-cost prioritization of image blocks in wireless sensor networks for border surveillance
Journal of Network and Computer Applications
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In this paper, we present and evaluate a hardware solution for user-driven and packet loss tolerant image compression, especially designed to enable low power image compression and communication over wireless camera sensor networks (WCSNs). The proposed System-on-Chip is intended to be designed as a hardware coprocessor embedded in the camera sensor node. The goal is to relieve the node microcontroller of the image compression tasks and to achieve high-speed and low power image processing. The interest of our solution is twofold. First, compression settings can be changed at runtime (upon reception of a request message sent by an end user or according to the internal state of the camera sensor node). Second, the image compression chain includes a (block of) pixel interleaving scheme which significantly improves the robustness against packet loss in image communication. We discuss in depth the internal hardware architecture of the encoder chip which is planned to reach high performance running in FPGAs and in ASIC circuits. Synthesis results and relevant performance comparisons with related works are presented.