Extending synchronization constructs in openMP to exploit pipeline parallelism on heterogeneous multi-core

Authors:
Shigang Li;Shucai Yao;Haohu He;Lili Sun;Yi Chen;Yunfeng Peng
Affiliations:
University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China;University of Science and Technology Beijing, Beijing, China
Venue:
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Year:
2011

Citing 14
Cited 1

Defining and Supporting Pipelined Executions in OpenMP

WOMPAT '01 Proceedings of the International Workshop on OpenMP Applications and Tools: OpenMP Shared Memory Parallel Programming
Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study

ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
Decoupled Software Pipelining with the Synchronization Array

Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Automatic Thread Extraction with Decoupled Software Pipelining

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Chip multiprocessing and the cell broadband engine

Proceedings of the 3rd conference on Computing frontiers
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
A Proposal for Task Parallelism in OpenMP

IWOMP '07 Proceedings of the 3rd international workshop on OpenMP: A Practical Programming Model for the Multi-Core Era
OpenMP tasks in IBM XL compilers

CASCON '08 Proceedings of the 2008 conference of the center for advanced studies on collaborative research: meeting of minds
QR factorization for the Cell Broadband Engine

Scientific Programming - High Performance Computing with the Cell Broadband Engine
Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays

ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Multithreaded code from synchronous programs: extracting independent threads for OpenMP

Proceedings of the Conference on Design, Automation and Test in Europe
Implementing Parallel LU Factorization with Pipelining on a MultiCore Using OpenMP

CSE '10 Proceedings of the 2010 13th IEEE International Conference on Computational Science and Engineering
Support for OpenMP tasks on cell architecture

ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II

Automatic generation of software pipelines for heterogeneous parallel systems

SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

Quantified Score

Hi-index	0.00

Visualization

Abstract

The ability of expressing multiple-levels of parallelism is one of the significant features in OpenMP parallel programming model. However, pipeline parallelism is not well supported in OpenMP. This paper proposes extensions to OpenMP directives, aiming at expressing pipeline parallelism effectively. The extended directives are divided into two groups. One can define the precedence at thread level while the other can define the precedence at iteration level. Through these directives, programmers can establish pipeline model more easily and exploit more parallelism to improve performance. To support these directives, a set of runtime interfaces for synchronization are implemented on the Cell heterogeneous multi-core architecture using signal block communications mechanism. Experimental results indicate that good performance can be obtained from the pipeline scheme proposed in this paper compared to the naive parallel applications.