Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
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Three dimensional Network-on-Chip (3D NoC) architectures have evolved with a lot of interest to address the on-chip communication delays of modern SoC systems. However, the vertical interconnections between layers is more power and area hungry compared to 2D interconnections. In this paper we propose area efficient and low power heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D mesh topologies. Experimental results show a negligible penalty of up to 5% in average packet latency of 3D homogeneous NoC with bus hybrid routers. The heterogeneity however provides superiority of up to 67% and 19.7% in power and area efficiency of the NoC resources, respectively.