Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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In this contribution we apply a novel strategy for partial remapping to significantly enhance the reliability of coarse-grained reconfigurable architectures. If a component of the architecture is affected by a permanent error, it will be deactivated and the architecture is reconfigured to relinquish the concerned resource. This is achieved by spatially moving operations from defective to unused components. If no unused component is available, operations are additionally moved within time domain to free the required resources. In our experiments, we regard the failure of each single component in an array of processing elements. Depending on the resource usage of the application, between 70% and 100% of the defects can be tolerated. In average, the repair of one failure takes 36 seconds, and the clock frequency has to be reduced by just 0.8% to enable the execution of the changed application mapping.