Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
| Hi-index | 0.02 |
Future, ultra-miniaturized chip technologies will be increasingly susceptible against faults that result from production variability or emerge in the field, e.g. due to aging effects. To maintain viable yield and operational reliability, this contribution proposes a new set of methods for tolerating such faults through adaptive routing in networks on chip (NoCs). Differential Q routing is introduced as an efficient method to distribute information on deviations from an original topology. Arbitrary fault-free and faulty combinations of network and crossbar switch topologies are supported by computing topological information offline and synthesizing it into NoC switches. An optimizing, yet efficiently implemented routing algorithm utilizes this information to make distributed routing decisions that minimize expected path length under the constraint of avoiding faults.