YAML: a tool for hardware design visualization and capture
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Hardware Design and Petri Nets
Hardware Design and Petri Nets
UML-Based Analysis of Embedded Systems Using a Mapping to VHDL
HASE '99 The 4th IEEE International Symposium on High-Assurance Systems Engineering
Application of UML for hardware design based on design process model
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
UML for SOC Design
On the Pitfalls of UML 2 Activity Modeling
MISE '07 Proceedings of the International Workshop on Modeling in Software Engineering
Computing repair trees for resolving inconsistencies in design models
Proceedings of the 27th IEEE/ACM International Conference on Automated Software Engineering
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The continuous advances in manufacturing Integrated Circuits (ICs) enable complete systems on a single chip. However, the design effort for such System-on-Chip (SoC) solutions is significant. The productivity of the design teams currently lags behind the advances in manufacturing and this design productivity gap is still widening. One important reason is the lack of abstraction in traditional Hardware Description Languages (HDLs) like VHDL. The UML provides more abstract concepts for modeling behavior that can also be employed for hardware design. In particular, the new UML Activity semantics fit nicely with the inherent data flow in hardware systems. Therefore, we introduce a UML-based design approach for complete SoC specification. Our approach enables generation of complete synthesizable HDL code. The equivalent hardware can be automatically generated using the existing tools chains. As an example, we outline Handel-C code generation for an MP3 decoder design.