Live range aware cache architecture

Authors:
Peng Li;Dongsheng Wang;Songliu Guo;Tao Tian;Weimin Zheng
Affiliations:
Research Institute of Information Technology, National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Research Institute of Information Technology, National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Research Institute of Information Technology, National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Research Institute of Information Technology, National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Research Institute of Information Technology, National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

Memory wall is always the focus of computer architecture research. In this paper, we observe that in computers with write-back cache, memory write operation actually lags behind write instruction commitment. By the time memory write operation executes, the data might already have gone out of its live range. Based on this observation, a novel Cache architecture called LIve Range Aware Cache (LIRAC) is proposed. LIRAC can significantly reduce the number of write operations with minimal hardware support. Performance benefits of LIRAC are evaluated by trace-based analysis using simplescalar simulator and SPEC CPU 2000 benchmarks. Our results show that LIRAC can eliminate 21% of write operations on average and up to 85% in the best case.