Register allocation on stream processor with local register file

Authors:
Nan Wu;Mei Wen;Ju Ren;Yi He;Chunyuan Zhang
Affiliations:
Computer School, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;Computer School, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;Computer School, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;Computer School, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China;Computer School, National University of Defense Technology, Chang Sha, Hu Nan, P.R. of China
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Abstract

Emerging stream processors for intensive computing use local register file to support ALUs array and use VLIW to explore instruction level parallelism. The current VLIW compilers for local register file such as ISCD work well on moderate media application without considering register allocation pressure. However, more complicated applications and optimizations that increase the size of the working set such as software pipelining make consideration of register pressure during the scheduling process. Based on ISCD complier, this paper presents two new techniques: spilling schedule and basic block repartition that compose a new schedule algorithm to alleviate register pressure. Experimental results show that it can deal with heavy workload application very well. The algorithm can also be applied to other microprocessors with the similar register architecture.