A computational logic handbook
A computational logic handbook
Extended static checking for Java
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Optimizing Supercompilers for Supercomputers
Optimizing Supercompilers for Supercomputers
Dynamic Logic
A Dynamic Logic for the Formal Verification of Java Card Programs
JavaCard '00 Revised Papers from the First International Workshop on Java on Smart Cards: Programming and Security
Software Analysis and Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Customised Induction Rules for Proving Correctness of Imperative Programs
SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Rippling: meta-level guidance for mathematical reasoning
Rippling: meta-level guidance for mathematical reasoning
Termination proofs for systems code
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Time and Parallel Processor Bounds for Fortran-Like Loops
IEEE Transactions on Computers
Sequential, parallel, and quantified updates of first-order structures
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
An improved rule for while loops in deductive program verification
ICFEM'05 Proceedings of the 7th international conference on Formal Methods and Software Engineering
Verification of safety properties in the presence of transactions
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Formalisation and verification of java card security properties in dynamic logic
FASE'05 Proceedings of the 8th international conference, held as part of the joint European Conference on Theory and Practice of Software conference on Fundamental Approaches to Software Engineering
Verification by parallelization of parametric code
Algebraic and proof-theoretic aspects of non-classical logics
Journal of Symbolic Computation
Sequential, parallel, and quantified updates of first-order structures
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Hi-index | 0.00 |
Loops are a major bottleneck in formal software verification, because they generally require user interaction: typically, induction hypotheses or invariants must be found or modified by hand. This involves expert knowledge of the underlying calculus and proof engine. We show that one can replace interactive proof techniques, such as induction, with automated first-order reasoning in order to deal with parallelizable loops, where a loop can be parallelized whenever it avoids dependence of the loop iterations from each other. We develop a dependence analysis that ensures parallelizability. It guarantees soundness of a proof rule that transforms a loop into a universally quantified update of the state change information represented by the loop body. This makes it possible to use automatic first order reasoning techniques to deal with loops. The method has been implemented in the KeY verification tool. We evaluated it with representative case studies from the Java Card domain.