Distributed Controller Synthesis for Local Specifications
ICALP '01 Proceedings of the 28th International Colloquium on Automata, Languages and Programming,
Synthesizing Distributed Systems
LICS '01 Proceedings of the 16th Annual IEEE Symposium on Logic in Computer Science
Complexity classification of network information flow problems
SODA '04 Proceedings of the fifteenth annual ACM-SIAM symposium on Discrete algorithms
LICS '05 Proceedings of the 20th Annual IEEE Symposium on Logic in Computer Science
SFCS '79 Proceedings of the 20th Annual Symposium on Foundations of Computer Science
Distributed reactive systems are hard to synthesize
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
IEEE Transactions on Information Theory
Natural Specifications Yield Decidability for Distributed Synthesis of Asynchronous Systems
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
Distributed synthesis for well-connected architectures
Formal Methods in System Design
Synthesis of Fault-Tolerant Distributed Systems
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
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We study the synthesis problem for external linear or branching specifications and distributed, synchronous architectures with arbitrary delays on processes. External means that the specification only relates input and output variables. We introduce the subclass of uniformly well-connected (UWC) architectures for which there exists a routing allowing each output process to get the values of all inputs it is connected to, as soon as possible. We prove that the distributed synthesis problem is decidable on UWC architectures if and only if the set of all sets of input variables visible by output variables is totally ordered, under set inclusion. We also show that if we extend this class by letting the routing depend on the output process, then the previous decidability result fails. Finally, we provide a natural restriction on specifications under which the whole class of UWC architectures is decidable.