Two-Level dynamic programming hardware implementation for real time processing

Authors:
Yong Kim;Hong Jeong
Affiliations:
Department of Electronic and Electrical Engineering, POSTECH, Pohang, Kyungbuk, South Korea;Department of Electronic and Electrical Engineering, POSTECH, Pohang, Kyungbuk, South Korea
Venue:
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Year:
2006

Citing 2
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A Comparative Study of Two Search Strategies for Connected Word Recognition: Dynamic Programming and Heuristic Search

IEEE Transactions on Pattern Analysis and Machine Intelligence
Fundamentals of speech recognition

Fundamentals of speech recognition

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Abstract

In this paper, we present an efficient architecture for connected speech recognition that can be efficiently implemented with FPGA. The architecture consists of newly derived two-level dynamic programming(TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the computational speed from avoiding propagation delays in multiplications. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33MHz.