Predicting MPEG execution times
SIGMETRICS '98/PERFORMANCE '98 Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Frame-based dynamic voltage and frequency scaling for a MPEG decoder
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
Proceedings of the 41st annual Design Automation Conference
Complexity Estimation of the H.264 Coded Video Bitstreams
The Computer Journal
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
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This paper proposes a novel power-aware scheme of H.264/AVC video player for the PAC SoC platform based on its modern dual-core architecture with DVFS capability. Energy/power is saved by the global view of power state transitions on the dual-core subsystem according to a user's behaviors of playing a video. When the user stays in continuous video decoding, a fine-grain power-aware scheme is devised to save the energy/power in advance. Especially the fine-grain model is suitable for any standard coded H.264/AVC video without extra modifications. We also discuss a workable reduction technique when imprecise video decoding time is permitted under soft real-time constraint. For a similar SoC platform with the dual-core architecture and DVFS capability, the idea presented here is, to the best of our knowledge, the first power-aware design of H.264/AVC video player