Design and implementation of frequency offset estimation, symbol timing and sampling clock offset control for an IEEE 802.11a physical layer

  • Authors:

  • Kwang-ho Chun;Seung-hyun Min;Myoung-ho Seong;Myoung-seob Lim

  • Affiliations:

  • The Faculty of Electronic & Information Eng., Chonbuk National Univ., Korea;The Faculty of Electrical & Computer Eng., Chungbuk National Univ., Korea;The Faculty of Electronic & Information Eng., Chonbuk National Univ., Korea;The Faculty of Electronic & Information Eng., Chonbuk National Univ., Korea

  • Venue:
  • ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
  • Year:
  • 2005

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Abstract

In this paper, the simulation and the design results about the algorithm of symbol timing recovery and frequency offset using the PLCP preamble, and sampling clock offset using the cyclic prefix in time domain for an IEEE 802.11a high-speed wireless LAN modem are presented. The algorithm of frequency offset estimation and compensation for making the frequency offset converge fast below the allowable limit is proposed. For the efficient implementation of the algorithm, the method that H/W size can be reduced up to 80% in the cross correlation block is designed and the method for the high speed processing of the divider block in the phase estimation is designed. And the newly proposed sampling clock offset estimation method makes it possible to adjust the optimum sampling point.