The input/output complexity of sorting and related problems
Communications of the ACM
A bridging model for parallel computation
Communications of the ACM
LogP: a practical model of parallel computation
Communications of the ACM
A New Convex Hull Algorithm for Planar Sets
ACM Transactions on Mathematical Software (TOMS)
Convex hulls of finite sets of points in two and three dimensions
Communications of the ACM
Extending the Hong-Kung Model to Memory Hierarchies
COCOON '95 Proceedings of the First Annual International Conference on Computing and Combinatorics
QSM: A General Purpose Shared-Memory Model for Parallel Computation
Proceedings of the 17th Conference on Foundations of Software Technology and Theoretical Computer Science
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Provably good multicore cache performance for divide-and-conquer algorithms
Proceedings of the nineteenth annual ACM-SIAM symposium on Discrete algorithms
Fundamental parallel algorithms for private-cache chip multiprocessors
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures
A unified model for multicore architectures
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Foundations of Algorithms, Fourth Edition
Foundations of Algorithms, Fourth Edition
A bridging model for multi-core computing
Journal of Computer and System Sciences
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Nowadays, the evolution of multi-core architectures goes towards increasing the number of cores and levels of cache. Meanwhile, current typical parallel programming models are unable to exploit the potential of these processors efficiently. In order to achieve desired performance on these hardwares we need to understand architectural parameters appropriately and also apply them in algorithm design. Computational models such as Multi-BSP, illustrate these parameters and explain adequate methods for designing algorithms on multi-cores. One of the most applicable categories of problems is Divide-and-Conquer (DaC) that needs to be adapted by such model for implementing on these systems. In this paper, we have attempted to make a mapping between DaC tree and the Memory Hierarchy (MH) of multi-core processor. Multi-BSP model inspired us to introduce Multi-DaC programming model. Analogous to Multi-BSP analysis, lower bounds for communication and synchronization costs have been presented in the paper respecting DaC algorithms. This work is a step towards making multi-core programming easy and tries to obtain correct analysis of DaC algorithm behavior on multi-core architectures.