The analysis of hardware supported cache lock mechanism without retry

Authors:
Wonil Kim;Chuleui Hong;Yeongjoon Kim
Affiliations:
Dept. of Digital Contents, College of Electronics and Information Engineering, Sejong University, Seoul, Korea;Software School, Sangmyung University, Seoul, Korea;Software School, Sangmyung University, Seoul, Korea
Venue:
PDCAT'04 Proceedings of the 5th international conference on Parallel and Distributed Computing: applications and Technologies
Year:
2004

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Abstract

A lock mechanism is essential for synchronization on the multiprocessor systems. This paper proposes the new locking protocol, called WPV (Waiting Processor Variable) lock mechanism. It uses the cache state lock mechanism and has only one lock-read bus traffic. This paper also derives the analytical model of WPV lock mechanism as well as conventional memory and cache queuing lock mechanisms. The simulation results on the WPV lock mechanism show that access time is reduced comparing with the memory and queuing lock mechanism as the number of processors increases.