Round-robin arbiter design and generation
Proceedings of the 15th international symposium on System Synthesis
Designing Network On-Chip Architectures in the Nanoscale Era
Designing Network On-Chip Architectures in the Nanoscale Era
Towards efficient dynamic LLC home bank mapping with noc-level support
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
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Future chip multiprocessors will include tens and hundreds of cores organized in a tile-based design pattern. A built-in on-chip network (NoC) will be devoted to communicating processors and memory controllers among them. In these systems, a shared memory programming model is appealing since it simplifies programming efforts. However, a coherence protocol is needed to keep the data consistent all along the various levels of memory hierarchy. Usually an invalidation-based protocol is used where memory copies are invalidated before a processor writes on a memory block. Usually, all these control messages are delivered through the built-in NoC. In this paper we propose a NoC re-organization in which a small and fast control network is dedicated only to invalidation messages. By doing this, application traffic is alleviated and traffic overhead is significantly reduced. We explore different coherency protocol strategies to cope with an efficient mapping of network control messaging thus, optimizing the use of the control network. Simulation results demonstrate the impact of the control network over invalidation-based protocols. In particular, using this network is possible to lower the store miss latency by 20% and execution time.