Simulator for real-time abstract state machines

Authors:
Pavel Vasilyev
Affiliations:
Laboratory of Algorithmics, Complexity and Logic, Department of Informatics, University Paris-12, France
Venue:
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Year:
2006

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Abstract

We describe a concept and design of a simulator of Real-Time Abstract State Machines. Time can be continuous or discrete. Time constraints are defined by linear inequalities. Two semantics are considered: with and without non-deterministic bounded delays between actions. The simulator is easily configurable. Simulation tasks can be generated according to descriptions in a special language. The simulator will be used for on-the-fly verification of formulas in an expressible timed predicate logic. Several features that facilitate the simulation are described: external functions definition, delays settings, constraints specification, and others.