Formalization of fFSM model and its verification

Authors:
Sachoun Park;Gihwon Kwon;Soonhoi Ha
Affiliations:
Department of Computer Science, Kyonggi University, Kyonggi-Do, Korea;Department of Computer Science, Kyonggi University, Kyonggi-Do, Korea;Department of Computer Engineering, Seoul National University, Seoul, Korea
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

PeaCE(Ptolemy extension as a Codesign Environment) was developed for the hardware and software codesign framework which allows us to express both data flow and control flow. The fFSM is a model for describing the control flow aspects in PeaCE, but it has difficulties in verifying their specifications due to lack of their formality. Thus we propose the formal semantics of the model based on its execution steps. To verify an fFSM model, it is translated into SMV input language with properties to be checked, automatically. As a result, some important bugs such as race condition, ambiguous transition, and circular transition can be formally detected in the model.