A novel block-based motion estimation algorithm and VLSI architecture based on cluster parallelism

Authors:
Tie-jun Li;Si-kun Li
Affiliations:
Office 621, School of Computer Science, National University of Defense Technology, ChangSha, China;Office 621, School of Computer Science, National University of Defense Technology, ChangSha, China
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

Citing 3
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Abstract

This paper proposes a novel block-based motion estimation algorithm and the corresponding architecture based on cluster parallelism. In this algorithm, up to 18 predictors are employed to improve the encoding quality while the computation time is not increased compared with PMVFAST. Experiment results verify the superiority of the proposed algorithm and architecture. The PSNR improvement effect on PMVFAST is 8.14 times higher than that of existing enhanced algorithm EPZS. In particular, they greatly improve the encoding quality of video sequence with large or irregular motion. Designed and synthesized on SMIC 0.18um technology, the architecture works on the frequency of 200MHz. Its throughput is about 15 times higher than the well-known FS architecture with 16 PEs while it consumes only 9.1% memory bandwidth of the FS architecture.