IEEE Transactions on Parallel and Distributed Systems
Approximation algorithms for bin packing: a survey
Approximation algorithms for NP-hard problems
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
ipChinook: an integrated IP-based design framework for distributed embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
A Generalized Scheme for Mapping Parallel Algorithms
IEEE Transactions on Parallel and Distributed Systems
Packing Schemes for Gang Scheduling
IPPS '96 Proceedings of the Workshop on Job Scheduling Strategies for Parallel Processing
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Most of the new embedded systems require high performance pro- cessors at low power. To cater to these needs, most semiconductor companies are designing multi-core processors, also known as chip-multiprocessors, while some are developing multi-chip boards with existing multi-core processors. Developing applications on these powerful architectures require specialized tools to obtain the optimum performance. Most applications running on these processors not only require high processing power, but also have tight resource constraints. For both, chip-multiprocessors and multi-chip boards, one faces some common problems while developing applications for them. To meet this end, we have developed tools to model high-performance embedded applications on these complex high-end systems. We have integrated these tools in the modeling framework of MILAN, and have modeled a real application, Mpeg-2 Audio Video Decoder. For validation we have used Cradle Technologies MDSP multi-core chip as the target processor.