Model checking of OSEK/VDX OS design model based on environment modeling
ICTAC'12 Proceedings of the 9th international conference on Theoretical Aspects of Computing
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Formal methods are effective techniques for automating software verifications to satisfy quality and reliability. However, the application of these techniques within industrial settings remains limited due to the complexity of produced models. Context-aware verification can circumvent this complexity by reducing the scope of the verification to some specific environmental conditions. We previously proposed a Context Description Language (CDL) to facilitate the formalization of requirements and contexts. However, the number of CDL models required to precisely formalize contexts grow rapidly according to the complexity of the system and manually writing CDL models is difficult and error prone task. In this paper, we propose a tool-supported framework that assists engineers in describing system contexts. We extended UML use cases with scenarios descriptions and we linked a domain specification vocabulary to automatically generate CDL models. An industrial case study is presented to illustrate the effectiveness of our approach.