CPACT - The conditional parameter adjustment cache tuner for dual-core architectures

Authors:
Marisha Rawlins;Ann Gordon-Ross
Affiliations:
Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA;Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA
Venue:
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Year:
2011

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Abstract

Cache tuning reveals substantial energy savings for single-core architectures, but has yet to be explored for multi-core architectures. In this paper we explore level one (L1) data cache tuning in a heterogeneous dual-core system where each data cache can have a different configuration. We show that L1 data cache tuning in a dual-core system achieves 25% average energy savings, which is comparable to single-core data cache tuning. We present the dual-core tuning heuristic CPACT, which finds cache configurations within 1% of the optimal configuration while searching only 1% of the design space. Finally, we provide valuable insights on core-interactions and data coherence revealed when tuning the multithreaded SPLASH-2 benchmarks.