FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Authors:
Jeich Mar;Chi-Cheng Kuo;Shih-Hao Chou
Affiliations:
Department of Communications Engineering, Yuan-Ze University, Taoyuan, Republic of China 320;Department of Communications Engineering, Yuan-Ze University, Taoyuan, Republic of China 320;Department of Communications Engineering, Yuan-Ze University, Taoyuan, Republic of China 320
Venue:
Journal of Signal Processing Systems
Year:
2012

Citing 3
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OFDM Wireless LANs: A Theoretical and Practical Guide
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Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)

Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology)

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Abstract

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.