Comparison of bit serial computation with bit parallel computation for reconfigurable processor

  • Authors:
  • Kazuya Tanigawa;Ken’ichi Umeda;Tetsuo Hironaka

  • Affiliations:
  • Graduate School of Information Sciences, Hiroshima City University, Asaminami-ku, Hiroshima, Japan;Graduate School of Information Sciences, Hiroshima City University, Asaminami-ku, Hiroshima, Japan;Graduate School of Information Sciences, Hiroshima City University, Asaminami-ku, Hiroshima, Japan

  • Venue:
  • ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
  • Year:
  • 2010

Quantified Score

Hi-index 0.00

Visualization

Abstract

Most of reconfigurable processors are adopting bit-parallel computation. On executing a program on such a reconfigurable processor, since bit-parallel computation require more hardware than bit-serial one, programs are often divided into several configuration and executed sequentially, which cause large overhead on performance. To solve the problem, we have developed a reconfigurable processor based on bit-serial operation, which can execute more operations in a reconfigurable part enough to prevent such a division of configuration and keep the chip area small. This paper shows that a reconfigurable processor based on bit-serial computation achieves higher performance than the traditional one based on bit-parallel computation under the condition of same chip area, by the evaluation using median filter as benchmark program.