Two-level adaptive training branch prediction
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Dynamic history-length fitting: a third level of adaptivity for branch prediction
Proceedings of the 25th annual international symposium on Computer architecture
Variable length path branch prediction
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
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As modern microprocessros and embedded processors employ deeper pipelines and issue multiple instructions per cycle, accurate branch predictors become an essential part of processor architectures. In this paper, we introduce a history length adjustable gshare predictor for the high-performance embedded processors and show its low-level implementation. Compared to the previous gshare predictor, history length adjustable gshare predictor selectively utilizes the branch history, resulting in substantial improvement in branch prediction accuracy.