Core integration: overview and challenges
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
False Sharing and Spatial Locality in Multiprocessor Caches
IEEE Transactions on Computers
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Transaction level modeling in practice: motivation and introduction
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Multicore architectures have become ubiquitous in the recent years. Yet, traditional serial programming techniques cannot exploit their potential because they do not express the dependencies of the tasks clearly rendering them unsuitable for any system which can execute tasks in parallel. We present a methodology which enables designers to explicitly and separately express function, communication and platform aspects. The approach allows to explore all aspects of a system without even building virtual prototypes or platform-dependent code. A bottleneck analysis and resolution leads to a well matched hardware/software partitioning as a basis for subsequent HW and SW design.