Tools for verification and validation

Authors:
Bruno Bouyssounouse;Joseph Sifakis
Affiliations:
Verimag Laboratory, Centre Equation, Gieres, France;VERIMAG, Centre Équation, Gières, France
Venue:
Embedded Systems Design
Year:
2005

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Abstract

Verification and validation consists in exploring the current design against side properties expressed as part of the requirements. Verification & validation can concern: 1. the specification level, at early stages of the design process, or 2. the embedded code, from C/Ada/Java, to assembly.