A FPGA architecture of blind source separation and real time implementation

Authors:
Yong Kim;Hong Jeong
Affiliations:
Department of Electronic and Electrical Engineering, POSTECH, Pohang, Kyungbuk, South Korea;Department of Electronic and Electrical Engineering, POSTECH, Pohang, Kyungbuk, South Korea
Venue:
IWINAC'05 Proceedings of the First international work-conference on the Interplay Between Natural and Artificial Computation conference on Artificial Intelligence and Knowledge Engineering Applications: a bioinspired approach - Volume Part II
Year:
2005

Citing 4
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Blind separation of delayed sources based on information maximization

ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06

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Abstract

Blind source separation(BSS) of independent sources from their convolutive mixtures is a problem in many real-world multi-sensor applications. However, the existing BSS architectures are more often than not based upon software and thus not suitable for direct implementation on hardware. In this paper, we present a new VLSI architecture for the blind source separation of a multiple input mutiple output(MIMO) measurement system. The algorithm is based on feedback network and is highly suited for parallel processing. The implementation is designed to operate in real time for speech signal sequences. It is systolic and easily scalable by simple adding and connecting chips or modules. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototyping with Xilinx FPGAs.