Data cache management using frequency-based replacement
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
An approximate analysis of the LRU and FIFO buffer replacement schemes
SIGMETRICS '90 Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems
The LRU-K page replacement algorithm for database disk buffering
SIGMOD '93 Proceedings of the 1993 ACM SIGMOD international conference on Management of data
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
IEEE Transactions on Computers
2Q: A Low Overhead High Performance Buffer Management Replacement Algorithm
VLDB '94 Proceedings of the 20th International Conference on Very Large Data Bases
The Multi-Queue Replacement Algorithm for Second Level Buffer Caches
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
Design and Optimization of Large Size and Low Overhead Off-Chip Caches
IEEE Transactions on Computers
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
IEEE Design & Test
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
The M5 Simulator: Modeling Networked Systems
IEEE Micro
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
CLOCK-Pro: an effective improvement of the CLOCK replacement
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
PowerNap: eliminating server idle power
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Architecting phase change memory as a scalable dram alternative
Proceedings of the 36th annual international symposium on Computer architecture
Scalable high performance main memory system using phase-change memory technology
Proceedings of the 36th annual international symposium on Computer architecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
PDRAM: a hybrid PRAM and DRAM main memory system
Proceedings of the 46th Annual Design Automation Conference
MN-Mate: Resource Management of Manycores with DRAM and Nonvolatile Memories
HPCC '10 Proceedings of the 2010 IEEE 12th International Conference on High Performance Computing and Communications
Power management of hybrid DRAM/PRAM-based main memory
Proceedings of the 48th Design Automation Conference
MN-GEMS: A Timing-Aware Simulator for a Cloud Node with Manycore, DRAM, and Non-volatile Memories
CLOUD '11 Proceedings of the 2011 IEEE 4th International Conference on Cloud Computing
Efficient page caching algorithm with prediction and migration for a hybrid main memory
ACM SIGAPP Applied Computing Review
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The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Thus, emerging technologies such as on-chip memory and nonvolatile memory (NVRAM) have led to a paradigm shift in computing architecture era. For instance, nonvolatile memories like PRAM can be viable DRAM replacements, achieving competitive speeds at lower power consumption. On-chip memory such as 3D-stacked memory can solve the limitation of memory bandwidth. The confluence of these trends offers a new opportunity to rethink traditional computing system and memory hierarchies. In an attempt to mitigate the energy and memory wall, we propose a new architecture with a hierarchical and a hybrid main memory for manycore system, termed MN-MATE. The hierarchical memory consists of on-chip memory, which is called M1 memory, and a conventional DRAM memory is replaced by a hybrid memory of DRAM and PRAM, called M2 memory. On the top of the system, we designed and evaluated efficient management techniques to achieve the high performance and the low energy usage, including hierarchical memory management, power-aware hybrid memory management, and file caching on a hybrid memory. Preliminary results show that these techniques can improve performance and reduce energy usage. As a case study, we introduce the MaaS (Matching-as-a-Service) application which requires the large amount of memory and high computing power.