Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform

  • Authors:
  • Kyu Ho Park;Sung Kyu Park;Hyunchul Seok;Woomin Hwang;Dong-Jae Shin;Jong Hun Choi;Ki-Woong Park

  • Affiliations:
  • KAIST;KAIST;KAIST;KAIST;KAIST;KAIST;KAIST

  • Venue:
  • Proceedings of the 2012 International Workshop on Programming Models and Applications for Multicores and Manycores
  • Year:
  • 2012

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Abstract

The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Thus, emerging technologies such as on-chip memory and nonvolatile memory (NVRAM) have led to a paradigm shift in computing architecture era. For instance, nonvolatile memories like PRAM can be viable DRAM replacements, achieving competitive speeds at lower power consumption. On-chip memory such as 3D-stacked memory can solve the limitation of memory bandwidth. The confluence of these trends offers a new opportunity to rethink traditional computing system and memory hierarchies. In an attempt to mitigate the energy and memory wall, we propose a new architecture with a hierarchical and a hybrid main memory for manycore system, termed MN-MATE. The hierarchical memory consists of on-chip memory, which is called M1 memory, and a conventional DRAM memory is replaced by a hybrid memory of DRAM and PRAM, called M2 memory. On the top of the system, we designed and evaluated efficient management techniques to achieve the high performance and the low energy usage, including hierarchical memory management, power-aware hybrid memory management, and file caching on a hybrid memory. Preliminary results show that these techniques can improve performance and reduce energy usage. As a case study, we introduce the MaaS (Matching-as-a-Service) application which requires the large amount of memory and high computing power.