Binary neural networks – a CMOS design approach

  • Authors:

  • Amol Deshmukh;Jayant Morghade;Akashdeep Khera;Preeti Bajaj

  • Affiliations:

  • Lecturer & Research Associate, Electronics Dept, G.H.Raisoni College of Engineering, Nagpur, India;Research Associate, G.H.Raisoni College of Engineering, Nagpur, India;Research Associate, G.H.Raisoni College of Engineering, Nagpur, India;Professor & Head, ETRX Dept, G.H.Raisoni College of Engineering, Nagpur, India

  • Venue:
  • KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
  • Year:
  • 2005

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Abstract

The proposed work includes CMOS design of a Neuron to generate binary logic Artificial Neural Network (ANN) as well as Multilayer Neural network. Several neural net chips exist on the market today. Some of these chips operate as analog devices by running below threshold on the transistors thereby gaining continuous properties instead of discrete properties afforded by CMOS transistor logic. In the current paper, authors have proposed a weighter circuit. It is designed with the help of NAND & XOR gates & binary connections are stored in flops. Both the gates provide more flexibility than the way the neuron deals with the input. Two-phase clocking with no overlap is used to ensure that all weights are properly shifted in without any data corruption. The same concept is extended to multilayer network.