Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
Statistical critical path analysis considering correlations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with two-sided constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel macromodel for power estimation in CMOS structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Corner-based Timing Analysis (CTA) becomes more and more pessimistic as feature size shrinks. This trend has motivated the development of Statistical Static Timing Analysis (SSTA). In this paper, we propose a new path-based SSTA framework that allows the estimation of path delay distributions and delay correlations by propagating iteratively mean and variance of cell delay. These moments, conditioned on input slope and output load values, are pre-characterized by an improved method: log-logistic distribution based input signals and inverters as output load. In applications, the delay gains of this SSTA framework with respect to CTA are shown to be significant. It is also highlighted that the discrepancy of critical paths orderings obtained by SSTA and CTA depends on two factors: cell-to-cell delay correlation and standard deviation of cell delay.