ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification of parameterized programs
Specification and validation methods
Abstracting WS1S Systems to Verify Parameterized Networks
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Beyond Parameterized Verification
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Verification of Parameterized Bus Arbitration Protocol
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Predicate Diagrams for the Verification of Reactive Systems
IFM '00 Proceedings of the Second International Conference on Integrated Formal Methods
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This paper presents a method for verifying universal properties of parameterized parallel systems using Parameterized Predicate Diagrams [10]. Parameterized Predicate Diagrams are diagrams which are used to represent the abstractions of such systems described by specifications written in temporal logic. This method presented here integrates deductive verification and algorithmic techniques. Non-temporal proof obligations establish the correspondence between the original specification and the diagram, whereas model checking can be used to verify properties over finite-state abstractions.