Two-dimensional fast cosine transform for Vector-STA architectures

Authors:
J. P. Robelly;A. Lehmann;G. Fettweis
Affiliations:
Vodafone Chair for Mobile Communications Systems, Technische Universität Dresden, Dresden, Germany;Vodafone Chair for Mobile Communications Systems, Technische Universität Dresden, Dresden, Germany;Vodafone Chair for Mobile Communications Systems, Technische Universität Dresden, Dresden, Germany
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

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Abstract

A vector algorithm for computing the two-dimensional Discrete Cosine Transform (2D-VDCT) is presented. The formulation of 2D-VDCT is stated under the framework provided by elements of multilinear algebra. This algebraic framework provides not only a formalism for describing the 2D-VDCT, but it also enables the derivation by pure algebraic manipulations of an algorithm that is well suited to be implemented in SIMD-vector signal processors with a scalable level of parallelism. The 2D-VDCT algorithm can be implemented in a matrix oriented language and a suitable compiler generates code for our family of STA (Synchronous Transfer Architecture) vector architectures with different amounts of SIMD-parallelism. We show in this paper how important speedup factors are achieved by this methodology.