Reconfigurable massively parallel computers
Reconfigurable massively parallel computers
Vision Chips
Associative Nets: A Graph-Based Parallel Computing Model
IEEE Transactions on Computers
Implementation and evaluation of a parallel architecture using asynchronous communications
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
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Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients to support regional computations. Asynchronism implies using combinatorial multi-input operators having an important hardware cost. To reduce it, we propose to use a connection network having a connectivity level greater than the mesh being mapped. This solution allows to use only 2-inputs asynchronous operators having a reduced hardware cost in each pixel. Examples and results will be presented on the examples of the regional sum algorithm computed over a 4-connectivity squared mesh connected with a 6-connectivity interconnection network, and the regional sum computed over a 6-connectivity squared mesh connected with a 8-connectivity interconnection network.