An experimental active memory based I/O subsystem

  • Authors:
  • Abhaya Asthana;Mark Cravatts;Paul Krzyzanowski

  • Affiliations:
  • AT&T Bell Laboratories, Murray Hill, New Jersey;AT&T Bell Laboratories, Murray Hill, New Jersey;AT&T Bell Laboratories, Murray Hill, New Jersey

  • Venue:
  • ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
  • Year:
  • 1994

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Abstract

We describe an I/O subsystem based on an active memory called SWIM, designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to communicate with a disk or a communication line through a backend port. The processing logic is specially designed to perform operations such as pointer dereferencing, memory indirection, searching and bounds checking efficiently. The I/O subsystem is built using an interconnected ensemble of such memory logic pairs. This allows a complex I/O task to be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control for higher level functions. This enables more powerful, scalable and robust designs for storage and communications subsystems that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year. We present the application of SWIM to three network functions that we have currently implemented: a national phone database server, a high performance IP router, and a call screening agent.