A case for the multithreaded processor architecture

Authors:
Ghulam Chaudhry;Xuechang Li
Affiliations:
Computer Engineering Research Laboratory, Department of Electrical and Computer Engineering, The University of Missouri at Columbia, 600 West Mechanic, Independence, MO;Computer Engineering Research Laboratory, Department of Electrical and Computer Engineering, The University of Missouri at Columbia, 600 West Mechanic, Independence, MO
Venue:
ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems
Year:
1994

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Abstract

As cache based shared-memory multiprocessors are scaled (the number of processors are increased), there will be an increase in the network latency, due to cache coherence and synchronization delays. These parameters can cause a significant drop in processor utilization. Once a process has remote procedure call or need data from remote side, the processor has to be idle or make context switch to load the next process in which the CPU (Central Processing Unit) time is wasted.By maintaining the multiple threads in the hardware, and switching among them, the multithreaded processor can overlap the waiting time for the synchronization delay so that it decreases the processor idle time.This correspondence describes the multithreaded processor architecture, in which there are a number of hardware contexts per processor. It uses coarsegrain method to schedule threads and two-phase waiting algorithm to synchronize the waiting threads. From this architecture, we can study how many hardware contexts are needed, so the processor utilization can be increased. Moreover, we can study the effect on the utilization by changing the cache miss ratio.