Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout-driven memory synthesis for embedded systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
OFDM for Wireless Multimedia Communications
OFDM for Wireless Multimedia Communications
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
Instrumentation Set-up for Instruction Level Power Modeling
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
UML for Embedded Systems Specification and Design: Motivation and Overview
Proceedings of the conference on Design, automation and test in Europe
Architectures and synthesis algorithms for power-efficient bus interfaces
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents the realization of an energy-aware system-on-chip that implements the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also covers critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral inter-faces were carefully combined and optimized for the targeted application, leading to a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 μm CMOS pro-cess and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW.