Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
PLC-Automata: A New Class of Implementable Real-Time Automata
ARTS '97 Proceedings of the 4th International AMAST Workshop on Real-Time Systems and Concurrent and Distributed Software: Transformation-Based Reactive Systems Development
Model-Based Implementation of Real-Time Systems
SAFECOMP '08 Proceedings of the 27th international conference on Computer Safety, Reliability, and Security
Translatable finite state time machine
SDL'07 Proceedings of the 13th international SDL Forum conference on Design for dependable systems
Formal modeling and synthesis of programmable logic controllers
Computers in Industry
Formal component-based modeling and synthesis for PLC systems
Computers in Industry
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The paper describes a formal method for automatic generation of programs for PLC controllers. The method starts from modeling the desired behavior of the system under design by means of a state machine with the ability to measure time and ends-up with a complete program written in a ladder diagram language. The model is formal, yet readable, and can be verified against the behavioral and safety requirements. The conversion of the model into a program is done automatically, which reduces the need for further program verification.