A digital processor for full calibration of pipelined ADCs

Authors:
Mohammad Fardad;Javad Frounchi;Ghader Karimian
Affiliations:
Microelectronic and Microsensor Research Laboratory, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran;Microelectronic and Microsensor Research Laboratory, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran;Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2012

Citing 4
Cited 0

First- and second-order methods for learning: between steepest descent and Newton's method

Neural Computation
Neural network design

Neural network design
Numerical Methods for Unconstrained Optimization and Nonlinear Equations (Classics in Applied Mathematics, 16)

Numerical Methods for Unconstrained Optimization and Nonlinear Equations (Classics in Applied Mathematics, 16)
A split-based digital background calibration technique in pipelined ADCs

IEEE Transactions on Circuits and Systems II: Express Briefs

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC.