Fractional full-search motion estimation VLSI architecture for H.264/AVC

Authors:
Chien-Min Ou;Huang-Chun Roan;Wen-Jyi Hwang
Affiliations:
Department of Electronics Engineering, Ching-Yun University, Chungli, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan;Graduate Institute of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan
Venue:
PSIVT'06 Proceedings of the First Pacific Rim conference on Advances in Image and Video Technology
Year:
2006

Citing 3
Cited 0

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
An efficient VLSI architecture for H.264 variable block size motion estimation

IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology

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Abstract

A novel half-pel full-search motion estimation VLSI architecture for H.264/AVC video encoders is presented in this paper. Based on the processing element arrays eliminating redundant data accesses and attaining 100 % utilization, the architecture can be implemented with low clock rate while having high processing throughput. Such an implementation is particularly suited to applications requiring real time operations with high compression efficiency and low power.