Model Checking - Timed UML State Machines and Collaborations
FTRTFT '02 Proceedings of the 7th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems: Co-sponsored by IFIP WG 2.2
vUML: A Tool for Verifying UML Models
ASE '99 Proceedings of the 14th IEEE international conference on Automated software engineering
A New Approach to Model Checking of UML State Machines
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
UML Automatic Verification Tool with Formal Methods
Electronic Notes in Theoretical Computer Science (ENTCS)
Towards checking parametric reachability for UML state machines
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
Parametric model checking with verICS
Transactions on Petri nets and other models of concurrency IV
Towards checking parametric reachability for UML state machines
PSI'09 Proceedings of the 7th international Andrei Ershov Memorial conference on Perspectives of Systems Informatics
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The paper presents a new approach to model checking of systems specified in UML. All the executions of an UML system (unfolded to a given depth) are encoded directly into a boolean propositional formula, satisfiability of which is checked using a SAT-solver. Contrary to other UML verification tools we do not use any of the existing model checkers as we do not translate UML specifications into an intermediate formalism. Moreover, we introduce some parametric extensions to the method. The method has been implemented as the (prototype) tool BMC4UML and several experimental results are presented.