A tightly coupled accelerator infrastructure for exact arithmetics

Authors:
Fabian Nowak;Rainer Buchty
Affiliations:
Chair for Computer Architecture, Karlsruhe Institute of Technology, Karlsruhe, Germany;Chair for Computer Architecture, Karlsruhe Institute of Technology, Karlsruhe, Germany
Venue:
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Year:
2010

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Abstract

Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In this domain, however, the problem of accuracy arises due to rounding of intermediate results. One solution is to avoid intermediate rounding by using exact arithmetic. The use of FPGAs as application-specific accelerators can speed up such operations compared to their software implementation. In this paper, we present a system approach employing state-of-the art FPGA and interconnection technology for exact arithmetic with double-precision operands, delivering up to 400M exact MACs/s in total and providing a speedup of up to 88 times over competing software implementations in the case of matrix multiplication.