FM8501: a verified microprocessor
FM8501: a verified microprocessor
Interactive Theorem Proving and Program Development
Interactive Theorem Proving and Program Development
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
IEEE Computer Architecture Letters
Formal Verification of a C-like Memory Model and Its Uses for Verifying Program Transformations
Journal of Automated Reasoning
Formal verification of a realistic compiler
Communications of the ACM - Barbara Liskov: ACM's A.M. Turing Award Winner
A trustworthy monadic formalization of the ARMv7 instruction set architecture
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
Handcrafted inversions made operational on operational semantics
ITP'13 Proceedings of the 4th international conference on Interactive Theorem Proving
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The simulation of Systems-on-Chip (SoC) is nowadays a hot topic because, beyond providing many debugging facilities, it allows the development of dedicated software before the hardware is available. Low-consumption CPUs such as ARM play a central role in SoC. However, the effectiveness of simulation depends on the faithfulness of the simulator. To this effect, we propose here to prove significant parts of such a simulator, SimSoC. Basically, on one hand, we develop a Coq formal model of the ARM architecture while on the other hand, we consider a version of the simulator including components written in Compcert-C. Then we prove that the simulation of ARM operations, according to Compcert-C formal semantics, conforms to the expected formal model of ARM. Size issues are partly dealt with using automatic generation of significant parts of the Coq model and of SimSoC from the official textual definition of ARM. However, this is still a long-term project. We report here the current stage of our efforts and discuss in particular the use of Compcert-C in this framework.