Hardware accelerator for vector quantization by using pruned look-up table

  • Authors:
  • Pi-Chung Wang;Chun-Liang Lee;Hung-Yi Chang;Tung-Shou Chen

  • Affiliations:
  • Telecommunication Laboratories, Chunghwa Telecom Co., Ltd., Taipei, Taiwan,R.O.C.;Telecommunication Laboratories, Chunghwa Telecom Co., Ltd., Taipei, Taiwan,R.O.C.;Department of Information Management, I-Shou University, Kaohsiung, Taiwan,R.O.C.;Institute of Computer Science and Information Technology, National Taichung Institute of Technology, Taichung, Taiwan,R.O.C.

  • Venue:
  • ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part IV
  • Year:
  • 2005

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Abstract

Vector quantization (VQ) is an elementary technique for image compression. However, searching for the nearest codeword in a codebook is time-consuming. The existing schemes focus on software-based implementation to reduce the computation. However, such schemes also incur extra computation and limit the improvement. In this paper, we propose a hardware-based scheme “Pruned Look-Up Table” (PLUT) which could prune possible codewords. The scheme is based on the observation that the minimum one-dimensional distance between the tested vector and its matched codeword is usually small. The observation inspires us to select likely codewords by the one-dimensional distance, which is represented by bitmaps. With the bitmaps containing the positional information to represent the geometric relation within codewords, the hardware implementation can succinctly reduce the required computation of VQ. Simulation results demonstrate that the proposed scheme can eliminate more than 75% computation with an extra storage of 128 Kbytes.