Validated code generation for activity diagrams

Authors:
A. K. Bhattacharjee;R. K. Shyamasundar
Affiliations:
Reactor Control Division, Bhabha Atomic Research Centre, Mumbai;School of Technology and Computer Science, Tata Institute of Fundamental Research, Mumbai
Venue:
ICDCIT'05 Proceedings of the Second international conference on Distributed Computing and Internet Technology
Year:
2005

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Abstract

Activity Diagram is an important component of the set of diagrams used in UML. The OMG document on UML 2.0 proposes a Petri net based semantics for Activity Diagrams. While Petri net based approach is useful and interesting, it does not exploit the underlying inherent synchronous concepts of activity diagrams. The latter can be effectively utilized for validated code generation and verification. In this paper, we shall capture activity diagrams in synchronous language framework to arrive at executional models which will be useful in model based design of software. This also enables validated code generation using code generation mechanisms of synchronous language environments such as Esterel and its programming environments. Further, the framework leads to scalable verification methods.