Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors

Optimization of instruction fetch mechanisms for high issue rates

ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture

The influence of branch prediction table interference on branch prediction scheme performance

PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques

The role of adaptivity in two-level adaptive branch prediction

Proceedings of the 28th annual international symposium on Microarchitecture

Correlation and aliasing in dynamic branch predictors

ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture

Multiple-block ahead branch predictors

Proceedings of the seventh international conference on Architectural support for programming languages and operating systems

Trace cache: a low latency approach to high bandwidth instruction fetching

Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture

A scalable front-end architecture for fast instruction delivery

ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture

Walk-Time Address Adjustment for Improving the Accuracy of Dynamic Branch Prediction

IEEE Transactions on Computers

Fetch directed instruction prefetching

Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

Improving BTB performance in the presence of DLLs

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Optimizations Enabled by a Decoupled Front-End Architecture

IEEE Transactions on Computers

Loop Termination Prediction

ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing