Improving Performance of Dynamic Programming via Parallelism and Locality on Multicore Architectures
IEEE Transactions on Parallel and Distributed Systems
Exploiting Internal Parallelism of Flash-based SSDs
IEEE Computer Architecture Letters
General Purpose Computing with Reconfigurable Acceleration
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
Hybrid Parallelism for Volume Rendering on Large-, Multi-, and Many-Core Systems
IEEE Transactions on Visualization and Computer Graphics
Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems
IEEE Embedded Systems Letters
Optimally Maximizing Iteration-Level Loop Parallelism
IEEE Transactions on Parallel and Distributed Systems
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In the embedded era, reconfigurable components comes in three forms of IP Intellectual Property cores i) Soft core ii) Firm core and iii) Hard Core. This paper presents a new technique of embedding multigrain parallel processing HPRC using FPGA in the CPU/DSP unit of OR1200 a soft-core RISC processor. The core performance is increased by placing a multigrain parallel processing HPRC internally in the Integer Execution Pipeline unit of the CPU/DSP core. Depending on the complexity/depth of the code, the dependency level of vertices DL were created and numbers of threads N were created to run the code parallel in HPRC. Multigrain parallel processing HPRC is achieved by two function i) HPRC_Parallel_Start to trigger the parallel thread ii) HPRC_Parallel_End to stop the thread. In the first phase of this paper a Verilog HDL functional code is developed and synthesised using XIINX ISE and in the second phase a CoreMark processor core benchmark is used to test the performance of the reconfigured IP soft core.