The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
The potential of the cell processor for scientific computing
Proceedings of the 3rd conference on Computing frontiers
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Cell broadband engine architecture and its first implementation: a performance view
IBM Journal of Research and Development
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimizing assignment of threads to SPEs on the cell BE processor
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
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Current multicores present themselves as symmetric to programmers with a bus as communication medium, but are known to be non-symmetric because their interconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermore, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.