Introducing the FPGA-Based hardware architecture of systemic computation (HAoS)

  • Authors:

  • Christos Sakellariou;Peter J. Bentley

  • Affiliations:

  • Department of Computer Science, University College of London, London, UK;Department of Computer Science, University College of London, London, UK

  • Venue:
  • MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
  • Year:
  • 2011

  • Natural born computing

    MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science

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Abstract

This paper presents HAoS, the first Hardware Architecture of the bio-inspired computational paradigm known as Systemic Computation (SC). SC was designed to support the modelling of biological processes inherently by defining a massively parallel non-conventional computer architecture and a model of natural behaviour. In this work we describe a novel custom digital design, which addresses the SC architecture parallelism requirement by exploiting the inbuilt parallelism of a Field Programmable Gate Array (FPGA) and by using the highly efficient matching capability of a Ternary Content Addressable Memory (TCAM). Basic processing capabilities are embedded in HAoS, in order to minimize time-demanding data transfers, while the optional use of a CPU provides high-level processing support. We demonstrate a functional simulation-verified prototype, which takes into consideration programmability and scalability. Analysis shows that the proposed architecture provides an effective solution in terms of efficiency versus flexibility trade-off and can potentially outperform prior implementations.