A sub-sampling 4.25GS/s 3-bit flash ADC with asymmetric spatial filter response

  • Authors:

  • Zhao Yi;Wang Shenjie;Hong Zhiliang

  • Affiliations:

  • State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China;State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2012

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Abstract

A sub-sampling 3-bit 4.25GS/s flash ADC with a novel averaging termination technique-asymmetric spatial filter response-in 0.13um CMOS for impulse radio ultra-wideband (IR-UWB) receiver is presented. In this design, a track and hold (T/H) circuit with self-biased buffer is used to compensate the degradation in amplitude when frequency increases to giga Hz. Averaging termination technique using asymmetric spatial filter response is proposed to relieve the termination offset of the flash ADC. A revised encoder scheme is adopted to solve the problem of different propagation delay. The measurement results reveal that the SFDR and SNDR of the ADC are 26.3dB and 18.4dB, respectively, even the input signal frequency is 4.2GHz. INL and DNL are measured improved to 0.11LSB and 0.18LSB, respectively, when asymmetric spatial filter is used. The power of ADC is 63mW and the active area is 0.49x0.72mm^2. The ADC achieves a figure of merit (FoM) of 2.2pJ/conversion-step.